M45PE40 Datasheet, PDF (23/35 Pages) STMicroelectronics – 4 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 33 MHz SPI Bus Interface

M45PE40
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V_CC) until V_CC reaches the
correct value:
– V_CC(min) at Power-up, and then for a further
delay of t_VSL
– V_SS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V_CC is less than the Power
On Reset (POR) threshold voltage, V_WI – all oper-
ations are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
tions until a time delay of t_PUW has elapsed after
the moment that V_CC rises above the V_WI thresh-
old. However, the correct operation of the device
is not guaranteed if, by this time, V_CC is still below
V_CC(min). No Write, Program or Erase instructions
should be sent until the later of:
– t_PUW after V_CC passed the V_WI threshold
– t_VSL after V_CC passed the V_CC(min) level
These values are specified in Table 6..
If the delay, t_VSL, has elapsed, after V_CC has risen
above V_CC(min), the device can be selected for
READ instructions even if the t_PUW delay is not yet
fully elapsed.
As an extra protection, the Reset (Reset) signal
can be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the device is in the following state:
– The device is in the Standby Power mode (not
the Deep Power-down mode).
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabilize the V_CC supply. Each de-
vice in a system should have the V_CC rail decou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V_CC drops from the operat-
ing voltage, to below the Power On Reset (POR)
threshold voltage, V_WI, all operations are disabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 19. Power-up Timing
VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
VWI
Reset State
of the
Device
tVSL
Read Access allowed
tPUW
Device fully
accessible
time
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