L6756D Datasheet, PDF (23/36 Pages) STMicroelectronics – 2/3/4 phase buck controller for VR10, VR11 and VR11.1 processor applications

L6756D
Output voltage positioning
5.5
Dynamic VID transitions
L6756D manages dynamic VID transitions that allow the output voltage to modify during
normal device operation for CPU power management purposes. OV and UV signals are
properly masked during every DVID Transition and they are re-activated with a 16 clock
cycle delay to prevent from false triggering.
When changing dynamically the regulated voltage (DVID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current I_DVID needs to
be delivered (especially when increasing the output regulated voltage) and it must be con-
sidered when setting the over current threshold of both the sections. This current results:
I_DVID
=
C_OUT
⋅
d_----V_{----O----U----T-}
dT_VID
Caution:
Caution:
where dV_OUT / dT_VID depends on the operative mode (typically externally driven).
Dynamic VID transition is managed by checking for VID code modifications (See Figure 8)
on the rising edge of an internal additional DVID-clock and waiting for a confirmation on the
following falling edge. Once the new code is stable, on the next rising edge, the reference
starts stepping up or down in LSB increments every two DVID-clock cycle until the new VID
code is reached.
DVID-clock frequency (F_DVID) is 1 MHz (Typ).
Overcoming the OC threshold during the DVID causes the device latch and disable.
If the new VID code is more than 1 LSB different from the previous, the device will execute
the transition stepping the reference with the DVID-clock frequency F_DVID until the new code
has reached. The output voltage rate of change will be of [LSB]mV * F_DVID!
Figure 8. DVID transitions
6)$#LOCK
6)$;=
)NT2EFERENCE
4_$6)$
4SW
6OUT
X3TEP6)$4RANSITION
6OUT3LOPE#ONTROLLEDBYINTERNAL
$6)$ #LOCK/SCILLATOR
4_6)$
X3TEP6)$4RANSITION
6OUT3LOPE#ONTROLLEDBYEXTERNAL
DRIVINGCIRCUIT4_6)$
T
T
T
T
!-V
23/36