TDA7564B Datasheet, PDF (22/34 Pages) STMicroelectronics – 4 x 50W multifunction quad power amplifier with built-in diagnostics features

I²C Bus interface
8
I²C Bus interface
TDA7564B
Data transmission from microprocessor to the TDA7564B and vice versa takes place
through the 2 wires I²C Bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
8.1
Data validity
As shown by Figure 30, the data on the SDA line must be stable during the high period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
8.2
Start and stop conditions
As shown by Figure 31 a start condition is a high to low transition of the SDA line while SCL
is HIGH. The stop condition is a low to high transition of the SDA line while SCL is high.
8.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
8.4
Acknowledge
The transmitter* puts a resistive high level on the SDA line during the acknowledge clock
pulse (see Figure 32). The receiver** the acknowledges has to pull-down (low) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable low during this clock
pulse.
* Transmitter
– master (μP) when it writes an address to the TDA7564B
– slave (TDA7564B) when the μP reads a data byte from TDA7564B
** Receiver
– slave (TDA7564B) when the μP writes an address to the TDA7564B
– master (µP) when it reads a data byte from TDA7564B
Figure 30. Data validity on the I²C Bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
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