TDA7404DTR Datasheet, PDF (22/35 Pages) STMicroelectronics – Car radio signal processor

I2C bus interface
5
I²C bus interface
TDA7404
5.1
Interface protocol
The interface protocol comprises:
● a start condition (S)
● a chip address byte (the LSB bit determines read / write transmission)
● a subaddress byte
● a sequence of data (N-bytes + acknowledge)
● a stop condition (P)
● the max. clock speed is 500 Kbits/s
Figure 17. Software specification
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
S 1 0 0 0 1 0 0 R/W
D99AU1044
MSB
LSB
MSB
ACK I3 I2 I1 I0 A3 A2 A1 A0 ACK
ACK
LSB
ACK P
S
R/W
ACK
P
= Start
= "0" -> Receive-Mode (Chip could be programmed by P)
"1" -> Transmission-Mode (Data could be received by P)
= Acknowledge
= Stop
5.2
Transmitted data (send mode)
MSB
LSB
X
X
X
X
X
X
X
SM
SM = Soft mute activated
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chipaddress.
5.3
22/35
Reset condition
A Power on reset is invoked if the supply voltage is below than 3.5V. After that the following
data is written automatically into the registers of all subaddresses:
MSB
LSB
1
1
1
1
1
1
1
0
The programming after POR is marked bold-face / underlined in the programming tables.