STPMS2L-PUR Datasheet, PDF (22/33 Pages) STMicroelectronics – Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA

Theory of operation
STPMS2
In this way it is possible to access 128 different combinations, which are controlled through
pins MS0, MS1, MS2 and MS3.
MS0 sets the operating mode and amplifier gain selection as described in Table 8.
For the STPMS2L:
● MS0=GND or CLK to select LPR (low precision); f_CLK = 1 MHz is the typical input clock
frequency and low power mode is selected.
● MS0=NCLK or VCC to select HPR (high precision): f_CLK = 2 MHz is the typical input
clock frequency and accuracy is enhanced.
For the STPMS2H, LPR mode is not used and the settings should be chosen between
MS0=NCLK or VCC. In this case, f_CLK = 4 MHz is typical.
The relative gain of the current channel is selectable between 2 or 16, which defines the
maximum differential voltage on the current channel to ± 300 mV or ± 37.5 mV, respectively.
The voltage channel gain setting is fixed at 2, which defines the maximum differential
voltage on the voltage channel inputs to ± 300 mV.
Table 8.
MS0
GND
CLK
NCLK
VCC
Precision mode and input amplifier gain selection
Mode
Description
0
LPR, amplifier GAIN selection g3 = 16
1
LPR, amplifier GAIN selection g0 = 2
2
HPR, amplifier GAIN selection g0 = 2
3
HPR, amplifier GAIN selection g3 = 16
MS1 defines the temperature compensation (TC) curve of the internal voltage reference of
the STPMS2L, as described in Table 9. This bootstrap function is not used with the
STPMS2H. The temperature-compensated reference voltage generator produces V_REF =
1.23 V. This generator is implemented as a band gap generator, whose temperature
compensation curve can be selected through the MS1 configuration pin.
Table 9.
MS1
GND
CLK
NCLK
VCC
TC of the band-gap reference
Mode
0
TC = 60 ppm/°C
1
Flattest TC = +30 ppm/°C
2
TC = +160 ppm/°C
3
TC = -160 ppm/°C
Description
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MS2 defines the outputs of the device:
The STPMS2 sends to the DAT and DATn pins the sigma-delta streams synchronous to the
CLK signal. The output mode can be configured according to Table 10 as follows:
● The output current channel's sigma-delta stream on DAT and the voltage channel's
sigma-delta stream on DATn
● Output multiplexed signals, so when CLK = 0, the current channel output sigma-delta
value is set on the DAT pin, and when CLK = 1, the voltage channel output sigma-delta
value is set on the DAT pin. The DATn pin tracks DAT, so DATn = ~DAT.
● Output current channel's sigma-delta stream on DAT and the current channel's sigma-
delta stream negated on DATn
Doc ID 16525 Rev 3