LNBH26LS Datasheet, PDF (22/33 Pages) STMicroelectronics – Dual LNBS supply and control IC with step-up and IC interface

I²C interface protocol
Bit
Bit 7
(MSb)
Name
N/A
LNBH26LS
CH Value
Description
0 DSQIN input pin is set to receive external DiSEqC envelope
TTL signal
0 Reserved. Keep to “0”.
N/A = reserved bit.
All bits reset to “0” at power-on.
Table 8: DATA 3 (read/write register. Register address = 0X4)
Bit
Name CH Value
Description
Bit 0 (LSb) N/A
A0
Reserved. Keep to “0”
Bit 1
N/A
0
Reserved. Keep to “0”
Bit 2
PCL-A
1
Pulsed (dynamic) LNB output current limiting is deactivated
0
Pulsed (dynamic) LNB output current limiting is activated
Bit 3
N/A
0
Reserved. Keep to “0”
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
PCL-B B 1
Pulsed (dynamic) LNB output current limiting is deactivated
0
Pulsed (dynamic) LNB output current limiting is deactivated
Bit 7 (MSb) N/A
0
Reserved. Keep to “0”
N/A = reserved bit.
All bits reset to “0” at power-on.
Table 9: DATA 4 (read/write register. Register address = 0X5)
Bit
Bit 0
(LSb)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Name CH Value
N/A
-0
Reserved. Keep to 0
Description
N/A
N/A
OLR
-0
-0
A/B 1
0
N/A
-0
N/A
-0
THERM A/B 1
Reserved. Keep to 0
Reserved. Keep to 0
In case of overload protection activation (OLF=1), all VSEL 1..4
bits are reset to “0” and LNB output (VOUT pin) is disabled. The
VSEL bits must be set again by the master after the overcurrent
condition is removed (OLF=0).
In case of overload protection activation (OLF=1) the LNB output
(VOUT pin) is automatically enabled as soon as the overload
condition is removed (OLF=0) with the previous VSEL bits
setting.
Reserved. Keep to 0
Reserved. Keep to 0
If thermal protection is activated (OTF=1), all VSEL 1..4 bits are
reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits
must be set again by the master after the overtemperature
condition is removed (OTF=0).
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