L6738A Datasheet, PDF (22/32 Pages) STMicroelectronics – Embedded bootstrap diode

Application details
9
Application details
L6738A
9.1
Compensation network
The control loop shown in Figure 9 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, an offset resistor between FB node and
GND can be neglected in control loop calculation).
Error amplifier output is compared to the oscillator sawtooth waveform to provide a PWM
signal to the driver section. The PWM signal is then transferred to the switching node with
V_IN amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and V_OUT. This function has a double pole at frequency F_LC depending on the L-C_OUT
resonance and a zero at F_ESR depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage V_IN divided by the peak-to-peak oscillator voltage
∆V_OSC.
Figure 9. PWM control loop
V_IN
OSC
∆V_OSC
_
+
PWM
COMPARATOR
ERROR
AMP LIFIE R
+
_
V_REF
R_FB
L
R
C_OUT
ESR
V _OUT
C_F
R_F
C_P
C_S
Z_F
R_S
Z_FB
The compensation network closes the loop joining V_OUT and EA output with transfer
function ideally equal to -Z_F/Z_FB.
Compensation goal is to close to the control loop assuring high DC regulation accuracy,
good dynamic performance and stability. To achieve this, the overall loop needs high DC
gain, high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F_0dB) can be fixed choosing the right R_F/R_FB ratio, however, for
stability, it should not exceed F_SW/2π. To achieve a good phase margin, the control loop gain
has to cross the 0dB axis with -20dB/decade slope.
For example, Figure 10 shows an asymptotic bode plot of a type III compensation.
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Doc ID 18134 Rev 2