AN2556 Datasheet, PDF (22/35 Pages) STMicroelectronics – Porting an application from the ST10F269Zx to the ST10F273Z4

New features
AN2556
2.3.1
2.3.2
Table 13. X-Interrupt detailed mapping (continued)
XP0INT
XP1INT
I2C Transmit
X
X
I2C Error
SSC1 Receive
SSC1 Transmit
X
X
X
X
SSC1 Error
ASC1 Receive
X
X
ASC1 Transmit
X
X
ASC1 Transmit Buffer
ASC1 Error
X
X
PLL Unlock / OWD
PWM1 Channel 3...0
XP2INT
X
X
X
X
X
X
X
XP3INT
X
X
X
X
X
Hardware impacts
None.
Software impacts
The XIRxSEL registers must be configured. If none of the new X-Peripherals are used, that
is, only the X-Peripherals that were already present on ST10F269Zx are used, the following
values must be programmed:
● XIR0SEL = 0x0100, only CAN1 interrupt is enabled and can generate an interrupt to
the ST10 through XP0IC.
● XIR1SEL = 0x0100, only CAN2 interrupt is enabled and can generate an interrupt to
the ST10 through XP1IC.
● XIR2SEL = 0x0, not used.
● XIR3SEL = 0x2000, only PLL unlock interrupt is enabled and will generate an interrupt
to the ST10 through XP3IC.
Then, in the interrupt routines associated with the XPxIC, the respective flag in the XIRxSEL
register must be cleared. Since the XIRxSEL registers are not bit addressable, a pair of
registers (a pair for each XIRxSEL) is provided to allow setting and clearing the bits of
XIRxSEL without risking overwriting requests coming after reading the register and before
writing it. Therefore the following registers must be written to clear the flags:
● In the CAN1 interrupt routine, XIR0CLR (@ EB14h) = 0x0001.
● In the CAN2 interrupt routine, XIR1CLR (@ EB24h) = 0x0001.
● In the PLL unlock interrupt routine, XIR3CLR (@ EB44h) = 0x0020.
Additional information on the X-Interrupt multiplexer structure
Figure 1 on page 17 shows that the X-Interrupt sources are connected to the interrupt
request flag of the XIRxSEL registers and to the XPxIR request flag via an AND gate with
22/35