M41ST95W Datasheet, PDF (21/35 Pages) STMicroelectronics – 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor

M41ST95Y*, M41ST95W
Power-on Reset
The M41ST95Y/W continuously monitors V_CC.
When V_CC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for t_REC after V_CC passes V_PFD (max).
The RST pin is an open drain output and an appro-
priate pull-up resistor should be chosen to control
rise time.
Reset Input (RSTIN1 and RSTIN2)
The M41ST95Y/W provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table 7 and Fig-
ure 16 illustrate the AC reset characteristics of this
function. Pulses shorter than t_RLRH1 and t_RLRH2
will not generate a reset condition. RSTIN1 and
RSTIN2 are each internally pulled up to V_CC
through a 100kΩ resistor.
Figure 16. RSTIN1 and RSTIN2 Timing Waveforms
RSTIN1
RSTIN2
RST ⁽¹⁾
tRLRH1
tRLRH2
tR1HRH
tR2HRH
Note: 1. Open Drain Output
AI03665
Table 7. Reset AC Characteristics
Symbol
Parameter⁽¹⁾
Min
Max
Unit
t_RLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
t_RLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
t_R1HRH(4)
RSTIN1 High to RST High
96
98
ms
t_R2HRH(4,5)
RSTIN2 High to RST High
96
98
ms
Note: 1. Valid for Ambient Operating Temperature: T_A = –40 to 85°C; V_CC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see Table 8., page 23)
5. After crystal oscillator has started
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