AN2960 Datasheet, PDF (21/41 Pages) STMicroelectronics – ultra compact linear accelerometer

AN2960
About control registers
Figure 10 shows the block diagram of the digital processing chain and the related control
signals.
Figure 10. Digital processing chain block diagram
Offset
Adjustment
Block
HP Filter
HP_FILTER_RESET
Digital Processing Chain
0
1
CTRL_REG3(FDS)
0
Interrupt Generator
(FF_WU 1)
1
CTRL_REG2(HP FF_WU1)
Regs Array
Output regs
SRC reg 1
0
Interrupt Generator
(FF_WU 2)
1
CTRL_REG2(HP FF_WU2)
SRC reg 2
6.3
CTRL_REG3 (22h)
Control register #3.
IHL
PP_OD I²CFG2 I²CFG1 I²CFG0 I1CFG2 I1CFG1 I1CFG0
IHL
PP_OD
I²CFG2,
I²CFG0
I1CFG2,
I1CFG0
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
Push-pull/open drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Interrupt 2 configuration bits. Default value 000.
(see table below)
Interrupt 1 configuration bits. Default value 000.
(see table below)
Doc ID 15557 Rev 1
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