ADE3000 Datasheet, PDF (21/88 Pages) STMicroelectronics – LCD Display Engines with Integrated DVI, ADC and YUV Ports

ADE3XXX
Line Lock PLL Block
Table 7: Line Lock PLL Registers (Sheet 3 of 4)
Register Name
LLK_PLL_TC_BLS
LLK_PLL_TC_AEK
LLK_PLL_TC_BEK
LLK_PLL_TC_ALK
LLK_PLL_TC_BLK
LLK_PLL_TC_SLOW_TOL
Addr
0x0812
0x0813
0x0814
0x0815
0x0816
0x0817
LLK_PLL_TC_SLOW_LINE_NB
LLK_PLL_LOCK_TOL
0x0818
0x0819
LLK_PLL_LOCK_LINE_NB
LLK_PLL_PH_OFFSET
0x081A
0x081B
LLK_PLL_PH_OFFSET_EN
LLK_PLL_PULSE_HIGH_EXT
0x081C
0x081D
LLK_PLL_STAT_LINES_L
0x081E
LLK_PLL_STAT_LINES_H
0x081F
LLK_PLL_STAT_ERROR_INC_LOW 0x0820
Mode Bits
[7:6]
R/W
[5:0]
[7:4]
R/W
[3:0]
[7:4]
R/W
[3:0]
[7:6]
R/W
[5:0]
[7:6]
R/W
[5:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7]
[6:0]
R/W
[7]
[6:3]
R/W
[2:0]
R/W
[7:0]
R/W
[7:0]
[7:0]
Default
Description
0x20
Reserved
Slow Time Constant B Linear
Reserved
0x6
Lock Time Constant A Exponent
0x6
0x20
Reserved
Lock Time Constant B Exponent
Reserved
Lock Time Constant A Linear
0x20
0x80
0x10
0x20
0x30
Reserved
Lock Time Constant B Linear
More than SLOW_LINE_NB lines with a
phase error less than the SLOW_TOL will
set the slow status bit, and the PLL will work
with the slow time constant.
One or more lines with a phase error more
than SLOW_TOL will reset the slow status
bit, and the PLL will work with the fast time
constant.
LSB of SLOW_TOL is approx. 200ps.
More than LOCK_LINE_NB lines with a
phase error less than the LOCK_TOL will
set the lock status bit, and the PLL will work
with the lock time constant.
One or more lines with a phase error more
than LOCK_TOL will reset the lock status
bit, and the PLL will work with the slow time
constant.
LSB of LOCK_TOL is approx. 200 ps.
0x0
Phase Adjustment.
The maximum phase offset value is equal to
PHASE_RATE[31:21] or 0x40, whichever is
higher.
0x0
Phase Enable
0x0
0x0
0x10
Reserved
0: no pulse extend
1: extend pulse (normal)
Reserved
Pulse Extend Amount
0x0: Minimum
0x7: Maximum (Normal)
Number of lines to statistically analyze.
Reserved
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