STV9212 Datasheet, PDF (20/34 Pages) STMicroelectronics – Video Processor for CRT Monitors with PictureBooST

I²C-Bus Interface Specifications
3 I²C-Bus Interface Specifications
STV9212
The device is compatible to general I²C-bus specification. Its slave write address is DCh.
Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control
register map is given in Table 4.
Bold weight denotes default values assumed at power-on reset. The power-on reset is effected
every time that the supply voltage on VCCA pin drops below V_PORTH threshold (Refer to electrical
specifications).
In order to ensure compatibility with future devices, all “Reserved” bits are to be set to 0 once
uploaded by the control software.
Table 4: I²C-Bus Register Map
Sad b7
01
1
02
1
03
1
04
1
05
1
06
0
07
0
OCPTG
08 0:BLK
1:ICP
ASTBY
09 0:Normal
1:Standby
0A
1
0B
1
0C
1
PASTBY
0D 0:Normal
1:Standby
VIP
0E 0:0.2V
1:0.4V
PBGEN
0F 0:Disable
1:Enable
PBVIVEN
10 0:Disable
1:Enable
b6
b5
b4
b3
b2
b1
b0
CRST
Reserved
0
0
0
0
0
0
0
BRIG
0
0
0
0
0
0
0
DRIVE1
Reserved
0
0
0
0
0
0
0
DRIVE2
Reserved
0
0
0
0
0
0
0
DRIVE3
Reserved
0
0
0
0
0
0
0
Reserved
BRIGRG
0
0
0
0
0
0
1
Reserved
OSDCRST
0
0
0
1
0
0
1
TST1
TST0
BCSC1
BCWDTH
BCEDGE BCSC0
0:Normal
1:Test
0:Normal
1:Test
0:Trig mode
1:HS pulse
0
1
0:Rising
1:Falling
0:HS trig
1:BLK trig
ABLEN Reserved
TST2
Reserved
MOD
SWBLK BLKPOL
0:Bl. disable
1:Bl. enable
0
0:Test
1:Normal
0
0:DC
1:AC
0:Disable
1:Enable
0:Non-inv.
1:Inverted
IBL1
0
0
0
0
0
0
0
IBL2
0
0
0
0
0
0
0
IBL3
0
0
0
0
0
0
0
Reserved
TST4
TST3
BW
0
0:Normal
1:Test
0:Normal
1:Test
1
0
0
0
IBOF
IBLRG
1
0
0
0
0
0
0:Wide
1:Narrow
PBINS Reserved
PBCRST
Reserved
PBBRIG
0:PB Pin
1:Perman.
0
0
1
0
0
1
PBVIVAM
Reserved
PBVIVTC
Reserved
0
1
0
1
0
0
0
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