STTS424E02_08 Datasheet, PDF (20/51 Pages) STMicroelectronics – Memory module temperature sensor with a 2 Kb SPD EEPROM

Temperature sensor registers
STTS424E02
Table 9. Configuration register bit definitions
Bit
Definition
Event mode
0 – 0 = Comparator output mode (this is the default).
– 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event polarity
1 – 0 = Active-low (this is the default).
– 1 = Active-high; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Critical Event only
2 ^{– 0 = Event output on alarm or critical temperature event (this is the default).}
– 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm
window lock bit is set, this bit cannot be altered until it is unlocked.
Event output control
3 – 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event status (read-only)⁽¹⁾
4 – 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
Clear Event (write-only)⁽²⁾
5 – 0 = No effect.
– 1 = Clears the active event in interrupt mode.
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
6 _{– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a}
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
7 _{– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a}
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
Shutdown mode
– 0 = TS is enabled (this is the default).
8 _{– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No}
event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is
unlocked. However, it can be cleared at any time.
Hysteresis enable (see Figure 8 and Table 10)
– 00 = Hysteresis is disabled.
10:9 – 01 = Hysteresis is enabled at 1.5°C.
– 10 = Hysteresis is enabled at 3°C.
– 11 = Hysteresis is enabled at 6°C.
1. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be
cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning).
2. Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always
return a logic '0' result.
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