STM32F031X4 Datasheet, PDF (20/106 Pages) STMicroelectronics – ARM-based 32-bit MCU with up to 32 Kbyte Flash, 9 timers, ADC and communication interfaces, 2.0 - 3.6 V

Functional overview
STM32F031x4 STM32F031x6
Table 6. Comparison of I²C analog and digital filters
Aspect
Analog filter
Digital filter
Pulse width of
suppressed spikes
Benefits
Drawbacks
≥ 50 ns
Available in Stop mode
Variations depending on
temperature, voltage, process
Programmable length from 1 to 15
I2Cx peripheral clocks
–Extra filtering capability vs.
standard requirements
–Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
Table 7. STM32F031x4/x6 I²C implementation
I²C features⁽¹⁾
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
1. X = supported.
3.14
Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds one universal synchronous/asynchronous receiver/transmitter
(USART1) which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA
SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock
domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
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