ST20-C1 Datasheet, PDF (20/205 Pages) STMicroelectronics – Instruction Set Reference Manual

3.3 Registers
An implementation of the ST20-C1 core may include a register cache. This provides a
mechanism to accelerate access to local work space without changing the
programmer’s model of how the work space operates or impacting either the excellent
code density or low interrupt latency associated with a stack-based instruction set.
3.3 Registers
This section introduces the ST20-C1 core registers that are visible to the programmer.
Seven registers, known as process state registers, define the local state of the
executing process. These registers are preserved through exceptions. One other
register is provided for performing input/output, and is not preserved through excep-
tions. All registers are 32-bit. Each instruction explicitly refers to specific registers , as
described in the instruction definitions.
The state of an executing process at any instant is defined b y the contents of the
machine registers listed in Table 3.1. The registers are illustrated in Figure 3.4 and
described in the rest of this section.
Register
Areg
Breg
Creg
Iptr
Status
Wptr
Tdesc
IOreg
Description
Evaluation stack register A
Evaluation stack register B
Evaluation stack register C
Instruction pointer register, pointing to the next instruction to be executed
Status register
Work space pointer, pointing to the stack of the currently executing process
Task descriptor
Input and output register
Table 3.1 Processor registers
ST20-C1 Core
Evaluation Stack
Areg
Breg
Creg
Status
IOReg
Task Descriptor
Tdesc
Instruction Pointer
Iptr
Memory
Task Control
Block
Program
Code
Workspace Pointer
Wptr
offset
base
Figure 3.4 Register set
Local
Program
Data
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