M45PE80 Datasheet, PDF (20/36 Pages) STMicroelectronics – 8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface

M45PE80
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all
bits inside the chosen page. Before it can be ac-
cepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Page is a
valid address for the Page Erase (PE) instruction.
Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16..
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Page Erase (PE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Page Erase cycle (whose du-
ration is t_PE) is initiated. While the Page Erase cy-
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Page Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
A Page Erase (PE) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Erase (PE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figure 16. Page Erase (PE) Instruction Sequence
S
0123456789
29 30 31
C
Instruction
24 Bit Address
D
23 22
210
MSB
AI04046
Note: Address bits A23 to A20 are Don’t Care.
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