L7986TA Datasheet, PDF (20/43 Pages) STMicroelectronics – 3 A step-down switching regulator

Application information
L7986TA
Equation 20
f_LC
=
----------------------------------------¹------------------------------------------ ,
2π ⋅
L ⋅ C_OUT ⋅
1 + --^E-----^S----^R----
R_OUT
f_zESR = ₂----_π-----_â‹------_E----_S-----_R1-----_â‹------_C-----_O----_U----_T--
Equation 21
6.4.1
Q
=
-----^R----^O-----^U----^T-----^â‹-----^L-----^â‹------^C-----^O----^U----^T-----^â‹------⁽--^R-----^O----^U----^T-----+-----^E----^S-----^R-----⁾
L + C_OUT ⋅ R_OUT ⋅ E SR
,
R_OUT
=
V_{-----O----U----T--}
I_OUT
As seen in Section 5.3, two different kinds of network can compensate the loop. In the
following two paragraphs the guidelines to select the type II and type III compensation
network are illustrated.
Type III compensation network
The methodology to stabilize the loop consists of placing two zeroes to compensate the
effect of the LC double pole, therefore increasing phase margin; then, to place one pole in
the origin to minimize the dc error on regulated output voltage; and finally, to place other
poles far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so a type III network is adopted to compensate
the loop.
In Figure 9 the type III compensation network is shown. This network introduces two zeroes
(f_Z1, f_Z2) and three poles (f_P0, f_P1, f_P2). They are expressed as:
Equation 22
f_Z1
=
--------------------------¹----------------------------,
2π ⋅ C₃ ⋅ (R₁ + R₃)
f_Z2
=
-----------------¹------------------
2π ⋅ R₄ ⋅ C₄
Equation 23
f_P0 = 0,
f_P1 = ₂----_π-----_â‹------_R--¹--₃-----_â‹-----_C-----₃- ,
f_P2 = -₂---_π-----_â‹------_R----₄-----_â‹-¹------_CC--------₄-_{4--------⋅-+----------CC}--------₅--₅--
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Doc ID 022098 Rev 3