AN4027 Datasheet, PDF (20/41 Pages) STMicroelectronics – This application note describes the EVL6699-150W-SR demonstration

Functional check
AN4027
optimize the design of the LLC converter and prevent capacitive mode operation that may
occur because of operation at too low input voltage.
The DELAY pin (#2) is zero, as it must be during normal operation, because it works during
the overcurrent protection operation. The DIS pin (#8) is used for open loop protection and
therefore, even in this case, its voltage is at ground level.
In Figure 17 the pin voltages relevant to the control part of the L6699 are reported: the
RFmin pin (#4) is a 2 V (typ.) reference voltage of the oscillator, the switching frequency is
proportional to the current flowing out from the pin. CSS pin (#1) voltage is the same value
as pin #4 because it is connected to the latter via a resistor (R44), determining the soft-start
frequency. A capacitor (C18) is also connected between the CSS pin and ground, to set the
soft-start time. At the beginning of L6699 operation the voltage on the CSS pin is at ground
level because C18 is discharged, then the CSS pin (#1) voltage increases according to the
time constant till the RFmin voltage level is reached. The STBY pin (#5) senses the
optocoupler voltage; once the voltage decreases to 1.25 V, both gate drivers stop switching
and the circuit works in burst mode. The CF pin (#3) is the controller oscillator; its ramp
speed is proportional to the current flowing out from the RFmin pin (#4). The CF signal must
be clean and undistorted to obtain correct symmetry by the half bridge current, and
therefore care must be taken in the layout of the PCB.
4.1
Startup
The waveforms relevant to the board startup at 90 V_ac and full load have been captured in
Figure 18. Note that the output voltage reaches the nominal value approximately 800 ms
after plug-in. The L6563H, HV PFC controller, has an embedded high-voltage startup
charging the V_cc capacitor by a constant current, ensuring a constant wake-up time. This
can be seen by comparing Figure 18 with Figure 19, relevant to a startup at 265 V_ac and no
load, the output voltage rises at the nominal level in the same time. In both conditions the
output voltage has no overshoot or dips.
Figure 18. Startup at 90 V_ac - full load
Figure 19. Startup at 265 V_ac - no load
CH1: C9 bulk voltage CH2: GD L6563H
CH3: +12 Vout
CH4: VCC L6563H
AM11411v1
CH1: C9 bulk voltage CH2: GD L6563H
CH3: +12 Vout
CH4: VCC L6563H
AM11412v1
In Figure 20 the salient waveforms in the resonant tank during start up of the LLC are
reported. In Figure 21 the detail of waveforms at the beginning of operation shows that the
resonant circuit is working correctly in zero voltage switching operation from the initial
cycles. In the L6699 a new startup procedure, called “safe-start”, has been implemented in
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