VS6524 Datasheet, PDF (2/3 Pages) STMicroelectronics – VGA Mobile Camera Module

VS6524
Figure 1. Application Diagram
VS6524
VGA Mobile
Camera Module
CLK
CE
SCL, SDA
D[7:0]
HSYNC
VSYNC
PCLK
FSO
Baseband
or
Application
Processor
Figure 2. Block diagram
CLK
CE
SCL
SDA
D[7:0]
HSYNC, VSYNC
PCLK
FSO
VS6524
PLL and Clock Management
Power Mgmt
Power-On Reset
Camera
Controller
640 x 480
Pixel array
1152 x 864
VDD
DGND
AVDD
AGND
Video
Processor
Column ADC
X Decoder
Line SRAM
Table 1. Technical Specifications
Active pixels
640H x 480V
Pixel size
3.6 x 3.6µm
Array size
2.38 x 1.77 mm
Color filter array
RGB Bayer
Exposure control
+120 dB
Analog gain
+24 dB (max)
Dynamic range
61 dB (typical)
Signal-to-noise Ratio
35 dB at 100 lux (typical)
Frame rate
1 to 30 Hz
Image format
VGA, QVGA, QQVGA,
subQCIF
Arbitrary cropping
Horizontal/vertical flipping
Pixel format
YUV 4:2:2
RGB 565, RGB 444
Raw Bayer 10-bit
Table 1. Technical Specifications
Video Interface
Clock input
Supply voltage
I/O voltage
Power consumption
Lens
Depth of field
TV distortion
Relative illumination
Package type
Package size
System attach
8-bit parallel video, hsync,
vsync
ITU-R BT.656-4 compliant,
24 MHz max
6.5 to 27 MHz square
13 MHz typ. (on-chip PLL)
2.4 to 3.0 V analog
1.8 or 2.8 V +/- 0.1 V
CMOS levels
Streaming 30 fps: 30 mA
max
Power down: 10 µA max.
2-element, 50° HFOV, F#
2.8
20 cm to infinite
< 1%
45% typ.
SmOP2
7.0 x 7.0 x 4.5 mm (wlh)
FPC with 20-pin B2B
connector, Molex 55560-
0201 or equivalent^a
a. Contact us for custom FPC designs and/or ZIF connector
variants
PART NUMBERING
Table 2. Order Codes
Part Number
Description
VS6524P02S
SmOP2 7.0 x 7.0 x 4.5 mm
FPC attach, tray packing
2/3