TDA8205 Datasheet, PDF (2/8 Pages) STMicroelectronics – NICAM QPSK DEMODULATOR

TDA8205
PIN ASSIGMENT
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin Name
GND
XC1
XC2
DF2
DF1
BGIN
IIN
AGC
VCC
VDD
LFIL1
RG
GND
RFIL1
RESET
VDD
SERI
DACDL
DACDR
GND
CK11648
Function
Ground
Optional Crystal
Optional Crystal
Data Filter 2 (eye monitor)
Data Filter 1 (eye monitor)
System B/G Input
System I Input
AGC Filter Capacitor
+12V Supply
+5V Supply
Left Filter 1 (J-17 De-emphasis)
Gain Setting Resistor for DAC
Ground
Right Filter 1 (J-17 De-emphasis)
Reset Chip
+5V Supply
Interchip Serial Bus Input
DAC Data Left Input
DAC Data Right Input
Ground
11.648MHz Clock Output
Pin No
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Name
CK728
NDO
TEST
MMO
GND
AOL
AOR
DC1
DC2
AMOL
AMOR
CAP
MAI
SAIL
SAIR
EAIL
EAIR
VCC
XK1
LF2
LF1
Function
728kHz Clock Intput
NICAM Data Output
To be connected to GND
Matrix Mute Out
Ground
Audio Output Left
Audio Output Right
Decoupling 1
Decoupling 2
Audio Mutable Output Left
Audio Mutable Output Right
Decoupling Capacitor
Mono Audio Input
Stereo Audio Input Left
Stereo Audio Input Right
External Audio Input Left
External Audio Input Right
+12V Supply
11.648MHz Crystal
Loop Filter 2
Loop Filter 1
BLOCK DIAGRAM
9 10 16 39 8
5 4 42
41 23 22 21 19 18
11
34 35 36 31 32 37 38
I_IN 7
BG _IN 6
SWITCH
AGC
QSPSK
DEMOD
CLOCK
& DATA
RECOVERY
TEST 24
RESET 15
DUAL FREQ
SYNTHESISER
TDA8205
1 13 20 26 2 3 40
GND GND GND GND XC1 XC2 XK1
DAC
DAC
12
RG
MUTE
LPF
SWITCH
MATRIX
SWITCH
27 AOL
28 AOR
29 DC1
LPF
30 DC2
25 MMO
14
33
RFIL1 CAP
SERIAL
INTERFACE
17
SERI
BLOCK DIAGRAM DESCRIPTION
The QPSK signal enters the IC via two inputs after
passing through two external bandpass filters at
the relevant frequencies of 6.552MHz and
5.85MHz for system I and B/G respectively. The
two inputs enter a source selection switch and pass
immediately to an AGC block which has a total
range of 40dB. The resulting levelled signal passes
2/8
to the QPSK demodulator which recovers the NI-
CAM 728Kb/s data stream by means of carrier and
clock recovery circuits.
Carrier recovery is achieved with a baseband re-
modulator which consists of a phase locked loop
with a switchable phase detector. This allows it to
lock to one of four possible phases of the QPSK