M27V401 Datasheet, PDF (2/15 Pages) STMicroelectronics – 4 Mbit 512Kb x8 Low Voltage UV EPROM and OTP EPROM

M27V401
Figure 2A. DIP Pin Connections
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
M27V401
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A18
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
AI01861
Figure 2B. LCC Pin Connections
A7
A6
A5
A4
A3 9
A2
A1
A0
Q0
1 32
M27V401
17
A14
A13
A8
A9
25 A11
G
A10
E
Q7
AI00696
Figure 2C. TSOP Pin Connections
A11
A9
A8
A13
A14
A17
A18
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
32 G
A10
E
Q7
Q6
Q5
Q4
8 M27V401 25 Q3
9
(Normal) _{24 VSS}
Q2
Q1
Q0
A0
A1
A2
16
17 A3
AI01156B
For applications where the content is programmed
only one time and erasure is not required, the
M27V201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V401 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V_PP and 12V on A9 for Electronic
Signature.
Read Mode
The M27V401 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t_AVQV) is equal to the delay from E to output
(t_ELQV). Data is available at the output after a delay
of t_GLQV from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t_AVQV-t_GLQV.
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