EVAL6472H Datasheet, PDF (2/11 Pages) STMicroelectronics – SPI with daisy chain feature

Board description
1
Board description
EVAL6472H
Table 1. EVAL6472H specifications
Parameter
Supply voltage (VS)
Maximum output current (each phase)
Logic supply voltage (VREG)
Logic interface voltage (VDD)
Low level logic input voltage
High level logic input voltage
Operating temperature
L6472H thermal resistance junction-to-ambient
1. All logic inputs are 5 V tolerant.
Figure 1. Jumpers and connectors location
FLAG LED
(Red)
BUSY LED
(Amber)
Application reference
area
Master SPI
connector
Value
8 to 45 V
3 A_r.m.s.
Externally supplied: 3.3 V
Internally supplied: 3 V typical
Externally supplied: 3.3 V or 5 V
Internally supplied: VREG
0V
VDD⁽¹⁾
-25 to +125 °C
21 °C/W typical
Power supply connector
(8 V - 45 V)
JP1: VDD supply from
master SPI connector
JP3: Daisy chain
termination
Slave SPI
connector
External switch connector
(SW input)
Motor supply voltage
compensation
partitioning regulation
(ADCIN input)
Phase A connector
JP2: VDD to VREG
connection
OSCIN/OSCOUT
connector
Phase B connector
AM10289V1
2/11
Doc ID 022980 Rev 1