TDA7512 Datasheet, PDF (19/42 Pages) STMicroelectronics – AM/FM CAR RADIO TUNER IC WITH INTELLIGENT SELECTIVITY SYSTEM ISS

TDA7512
1.8 I²C-Bus Interface
The TDA7512 supports the I²C-Bus protocol. This protocol defines any device that sends data onto the bus as
a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and
device being controlled is the slave. The master will always initiate data transfer and provide the clock to trans-
mit or receive operations.
1.8.1 Data Transition
Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL is HIGH
will be interpreted as START or STOP condition.
1.8.2 Start Condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level.
This "START" condition must precede any command and initiate a data transfer onto the bus. The device con-
tinuously monitors the SDA and SCL lines for a valid START and will not response to any command if this con-
dition has not been met.
1.8.3 Stop Condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH
level. This condition terminates the communication between the devices and forces the bus-interface of the de-
vice into the initial condition.
1.8.4 Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. During the
9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits of data.
1.8.5 Data Transfer
During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for prop-
er device operation the SDA line must be stable during the SCL LOW to HIGH transition.
1.8.6 Device Addressing
To start the communication between two devices, the bus master must initiate a start instruction sequence, fol-
lowed by an eight bit word corresponding to the address of the device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA7512 device type is fixed as "110001".
The next significant bit is used to address a particular device of the previous defined type connected to the bus.
The state of the hardwired PIN 41 defines the state of this address bit. So up to two devices could be connected
on the same bus. When PIN 41 is connected to VCC2 the address bit “1” is selected. In this case the AM part
doesn’t work. Otherwise the address bit “0” is selected (FM and AM is working). Therefor a double FM tuner
concept is possible.
The last bit of the start instruction defines the type of operation to be performed:
– When set to "1", a read operation is selected
– When set to "0", a write operation is selected
The TDA7512 connected to the bus will compare their own hardwired address with the slave address being
transmitted, after detecting a START condition. After this comparison, the TDA7512 will generate an "acknowl-
edge" on the SDA line and will do either a read or a write operation according to the state of R/W bit.
1.8.7 Write Operation
Following a START condition the master sends a slave address word with the R/W bit set to "0". The device will
generate an "acknowledge" after this first transmission and will wait for a second word (the word address field).
This 8-bit address field provides an access to any of the 32 internal addresses. Upon receipt of the word address
the TDA7512 slave device will respond with an "acknowledge". At this time, all the following words transmitted
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