TDA7400D Datasheet, PDF (19/28 Pages) STMicroelectronics – ADVANCED CAR SIGNAL PROCESSOR

Figure 18. Block Diagram of the Multipath Detector
TDA7400D
LEVEL
MP_IN
VDD
CHARGE
1 bit
BANDPASS
19KHz
RECTIFIER
GAIN
2 BITS
GAIN
2 BITS
to SB
-
int. INFLUENCE
MPOUT
47nF
D98AU857
By rectifying the MPX signal a further signal rep-
resenting the actual deviation is obtained. It is
used to increase the PEAK voltage. Offset and
gain of this circuit are programmable in 3 steps
with the bits D6 and D7 of the stereodecoder byte
(the first step turns off the detector, see fig. 15).
FUNCTIONAL DESCRIPTION OF THE MULTI-
PATH DETECTOR
Using the internal multipath detector the audible
effects of a multipath condition can be minimized.
A multipath condition is detected by rectifying the
19kHz spectrum in the fieldstrength signal.
An external capacitor is used to define the attack
and decay times (see block diagram fig. 23). the
MPOUT pin is used as detector output connected
to a capacitor of about 47nF and additionally the
MPIN pin is selected to be the fieldstrength input.
Using the configuration an external adaptation to
the user’s requiremet is given in fig.25.
Selecting the "internal influence" in the configura-
tion byte, the channel separation is automatically
reduced during a multipath condition according to
the voltage appearing at the MP_OUT pin. A
possible application is shown in fig. 26.
Programming
To obtain a good multipath performance an adap-
tation is necessary. Therefore tha gain of the
19kHz bandpass is programmable in four steps
as well as the rectifier gain. The attack and decay
times can be set by the external capacitor value.
QUALITY DETECTOR
The TDA7400D offers a quality detector output
which gives a voltage representing the FM recep-
tion conditions. To calculate this voltage the MPX
noise and the multipath detector output are
summed according to the following formula:
Quality = 1.6 (Vnoise -0.8V)+ a (REF5V- VMPOUT)
The noise signal is the PEAK signal without addi-
tional influences. The factor "a" can be pro-
grammed from 0.7 to 1.15. the output is a low im-
pedance output able to drive external circuitry as
well as simply fed to an A/D converter for RDS
applications.
TEST MODE
During the test mode which can be activated by
setting bit D0 of the testing byte and bit D5 of the
subaddress byte to "1" several internal signals
are available at the CASSR pin.
During this mode the input resistor of 100kOhm is
disconnected from the pin. The internal signals
available are shown in the software specification.
19/28