STM32F100RC Datasheet, PDF (19/98 Pages) STMicroelectronics – High-density value line, advanced ARM-based 32-bit MCU

STM32F100xC, STM32F100xD, STM32F100xE
Description
2.2.18
2.2.19
2.2.20
2.2.21
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
I^²C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Universal asynchronous receiver transmitter (UART)
The STM32F100xx value line embeds 2 universal asynchronous receiver transmitters
(UART4, and UART5).
The available UART interfaces support IrDA SIR ENDEC, the multiprocessor communication
mode, the single-wire half-duplex communication mode and have LIN Master/Slave
capability.
The UART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
The SPIs can be served by the DMA controller.
Doc ID 15081 Rev 7
19/98