STLC5445 Datasheet, PDF (19/23 Pages) STMicroelectronics – QUAD LINE FEED CONTROLLER

STLC5445
Parallel interface mode
In Parallel interface mode (PSC pin Low), for each of the four output drivers a dedicated activation pin is pro-
vided (ES0-ES3):
Each driver will unconditionally be switched off when its ESn is pushed Low.
If the Power on sequencer is not used, each driver will be switched on (under the supervision of the pre-
viously described Thermal monitoring block) when its ESn is pushed High.
If the Power on sequencer is activated the drivers' activation requests coming from the ESn inputs will
(under the supervision of the previously described Thermal monitoring block) be processed by the Pow-
er on sequencer block (see the previous Power on sequencer's description).
In Parallel interface mode a single status bit is provided for each of the four channels at the open drain NACK0
- NACK3 output pins. The NACKn bit is generated by OR combining the three previously described status de-
tector bits: CODn, POFn and the complemented TOR. This means that each NACKn bit goes in high impedance
state (bit=1 if a NACKn pull up is externally provided) when at least one of these conditions is verified:
The current on the relative line reaches the current limit programmed by the user (the NACKn High state
in this case will not be latched).
The chip's temperature reaches 130°C and the channel is in current limiting condition (the NACKn High
state will in this case be latched).
The chip's temperature reaches 160°C (in this case all the NACKn will go in High state, but only the
NACKn of the activated channels will be latched).
The line driver is in the power on phase (in this case the NACKn will remain in High state only for the
time during which its channel is in current limiting condition).
When the ESn input is set Low, the corresponding NACKn is always set to zero.
In Parallel interface mode the output pin INTN and the input pin ALE are not used (ALE must in this case be tied
High or Low).
MPI interface mode
In MPI mode (PSC pin High), the ALE and INTN pins become active and the pins NACK0-NACK3 and ES0-ES3
have a function that is completely different from that performed in Parallel mode:
The four NACK0-NACK3 pins become D0 -D3 and act as a bidirectional data bus with three state capa-
bility.
The four ES0-ES3 pins become respectively A0, CSN, RDN and WRN.
In MPI mode the above mentioned four bits data bus and three internal four bits registers, LER (Line Enable
Register), LEC (Line Enable Control) and IAR (Indirect Address Register) are used to perform the following op-
erations:
Channels' output drivers switch on and switch off.
Enabling/disabling of the INTN (interrupt) signal generation.
Status detector bits reading.
T bit reading (this bit is High only when the internal chip's temperature exceeds 160°C).
The read/write operations on the data bus can only be performed when the CSN (Chip Select) pin is Low since
when CSN is High the data bus is inactive (high impedance state).
The active Low RDN and WRN signals are used to perform the read and write operations on the registers se-
lected by the logic level applied at the A0 pin:
A0=0 selects: The IAR register if a write operation is performed (status detector bits type selection and
enabling/disabling of the INTN signal generation via the I bit).
The reading of the bits actually written in the IAR register if a read operation is performed.
A0=1 selects: The LER register if a write operation is performed (switch on and switch off requests pro-
gramming for the output drivers).
19/23