STCN75_08 Datasheet, PDF (19/35 Pages) STMicroelectronics – Digital temperature sensor and thermal watchdog

STCN75
Functional description
3.3
Note:
Serial interface
Writing to and reading from the STCN75 registers is accomplished via the two-wire serial
interface protocol which requires that one device on the bus initiates and controls all READ
and WRITE operations. This device is called the “master” device. The master device also
generates the SCL signal which provides the clock signal for all other devices on the bus.
These other devices on the bus are called “slave” devices. The STCN75 is a slave device
(see Table 9). Both the master and slave devices can send and receive data on the bus.
During operations, one data bit is transmitted per clock cycle. All operations follow a
repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.
There are no unused clock cycles during any operation, so there must not be any breaks in
the data stream and ACKs/NACKs during data transfers. Consequently, having too few clock
cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register
occurs. So, the entire word must be transferred out regardless of the superflous trailing
zeroes.
Table 9. STCN75 serial bus slave addresses
MSB
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
A2
A1
A0
R/W
3.4
3.4.1
3.4.2
3.4.3
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined (see Figure 5 on page 20):
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to Low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
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