STCF04TBR Datasheet, PDF (19/43 Pages) STMicroelectronics – High power white LED SuperCap™ driver with I²C interface

STCF04
Detailed description
8.1.10
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time is interpreted as a control signal.
Figure 7. Bit transfer
AM11867v1
8.1.11
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 8). The peripheral (STCF04) that acknowledges must
pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed must
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case, the master
transmitter can generate the STOP information in order to abort the transfer. The STCF04
does not generate the acknowledge bit if the V_I supply is below 2.7 V.
Figure 8. Acknowledge on I²C bus
8.1.12
Interface protocol
The interface protocol is composed of (Table 8):
- A START condition (START)
- A device address + R/W bit (read =1 / write =0)
- A register address byte
Doc ID 022927 Rev 3
19/43