ST72141K Datasheet, PDF (19/132 Pages) STMicroelectronics – 8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE

ST72141K
3.2 RESET MANAGER
The RESET block includes three RESET sources
as shown in Figure 11:
s External RESET source pulse
s Internal LVD RESET (Low Voltage Detection)
s Internal WATCHDOG RESET
Figure 11. Reset Block Diagram
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
A 4096 CPU clock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
RESET
V_DD
R_ON
f_CPU
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
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