M24128S-FCU Datasheet, PDF (19/40 Pages) STMicroelectronics – 128-Kbit serial IC bus EEPROM 4 balls CSP

M24128S-FCU M24128S-FCV
Instructions
5.2
Read operations
Read operations are performed independently of the Write protection state.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
#URRENT
!DDRESS
2EAD
Figure 8. Read mode sequences
!#+
./!#+
$EVSEL
$ATAOUT
27
2ANDOM
!DDRESS
2EAD
!#+
!#+
!#+
!#+
./!#+
$EVSEL
"YTEADDR
"YTEADDR
$EVSEL
$ATAOUT
27
27
5.2.1
3EQUENTIAL
#URRENT
2EAD
!#+
!#+
$EVSEL
$ATAOUT
27
!#+
./!#+
$ATAOUT.
3EQUENTION
2ANDOM
2EAD
!#+
!#+
!#+
!#+
!#+
$EVSEL
"YTEADDR
"YTEADDR
$EVSEL
$ATAOUT
27
27
!#+
./!#+
$ATAOUT.
!)D
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 8) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
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