L6000 Datasheet, PDF (19/24 Pages) STMicroelectronics – SINGLE CHIP READ & WRITE CHANNEL

Figure 2: Normalized block diagram for filter
L6000
Normalized for ω_c = 2Πf_c = 1
AN and AD are adjusted for a gain of 2 @ f = 0.67fc
to denormalized the frequency it is necessary to substitude
s
with
s
2Π
fc
Synthesizer phase comparator. The Frequency
Synthesizer VCO is fed to divide by M+1 counter,
and the counter output is the other phase compa-
rator input.
This develops the frequency:
Fout
=
(M
(N
+
+
1)
1)
FREF
Note : For the new value in the M and N registers to be transferred
to their respective counters, the VCO Center Frequency DAC register
must be loaded with its value. This means the normal order of register
writes to change the Frequency Synthesizer output frequency would
be:
1) Write M and/or N register with its ( their ) new value ( s ).
2) Write the VCO Center Frequency register with its new value.
The RREF is choosen to set the frequency range
of both the FDSVCO and the DSVCO.
CLOCKS AND MODES
WRITE READ VCO
GATE GATE REF
RRC DECCLK ENCCLK MODE
O
0 Fout/2 Fout/3 Fout/2 Fout/2 IDLE
O
1 DRD VCO/3 VCO/2 Fout/2 READ
1
0 Fout/2 Fout/3 Fout/2 Fout/2 WRITE
Notes: 1 Until the VCO locks to the new source, the VCO/2 entries
will be FREQ OUT TP/2.
2: Until the VCO locks to the new source, the VCO/3 entries will be
FREQ OUT TP/3
3: WRITE GATE = READ GATE = 1 is undefined and illegal
Data Separator
The data separator circuit is a complete 1.7 RLL
ENDEC data recovery circuit. In the read mode,
the circuit performs data synchronization, sync
field search and detect, address mark detect,
Read-back clock generation and data decoding.
In the write mode, the circuit converts NRZ data
into the ( 1.7 ) RLL format described in the Table
1, performs write precompensation, generates the
preamble field and inserts address marks as re-
quested.
The data rate used for recovery is determined by
the VCO Center Frequency DAC, otherwise
called the PLL Control DAC and the external re-
sistor RREF connected to the pin DS IREF and
Data Separator GND. The differential filter con-
nected to the pins DATA SEP FLT and DATA
SEP FLT determine the loop gain, bandwidth and
damping. A second order filter is recommended in
most systems, and the filter will determine the
system characteristics. The phase comparator of
the Data Separator PLL utilizes phase only com-
parisons when locked to the disk data stream,
only making a phase comparison when a data bit
is available. In the frequency comparison mode, a
phase compare is is done to every VCO transi-
tion. This latter is done whenever the PLL is pow-
ered on and data is NOT being read from the
disk. By acquiring both phase and frequency lock
to the input reference frequency and utilizing a
zero phase restart technique, VCO transients are
minimized and false lock to READ DATA is elimi-
nated. The two control inputs READ GATE and
WRITE GATE directly switch the operations of
the Data Separator. In addition, there are two fur-
ther submodes split between the Hard Sector
mode of operation and the Soft Sector. Hard Sec-
tor operation is selected by resetting the SOFT bit
control B register via the serial interface. The as-
sertion of READ GATE causes the Data Separa-
tor to enter the lock up sequence, and Read
mode. Read mode continues until READ GATE
deassertion. The assertion of WRITE GATE
causes the Separator to enter Write mode.
WRITE GATE should not be deasserted until the
last bit is written on the disk. Assertion of BOTH
signals at once is illegal and will lead to unpre-
dictable results.
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