AN3123 Datasheet, PDF (19/30 Pages) STMicroelectronics – Using the UART interfaces in the SPEAr embedded MPU family

AN3123
8
DMA interface
DMA interface
DMA allows devices to transfer data without subjecting the processor to a heavy overhead.
Otherwise, the processor would have to copy each piece of data from the source to the
destination, making it unavailable for other tasks.
SPEAr300 and SPEAr600 provide an ARM PrimeCell^® DMA controller (DMAC) able to
service up to 8 independent DMA channels for serial data transfers between single source
and destination (for example, memory-to-memory, memory-to-peripheral, peripheral-to-
memory, and peripheral-to-peripheral).
The UART provides a DMA Interface for connecting to a DMA controller. The DMA operation
of the UART is controlled through the UART DMA control register. When the UART is in
FIFO disabled mode (where both FIFOs act like a one-byte holding register), only DMA
single transfer mode can operate, since only one character can be transferred to or from the
FIFO at any time.
● For transmit:
DMA transfers data from a source address to the transmit FIFO. When the transmit
FIFO is full, then DMA goes into wait state. Then, the UART transmits the data from the
transmit FIFO to the destination address. When there is at least one empty location in
the transmit FIFO then DMA comes out of wait state and again starts transferring data
to the transmit FIFO. In transmit mode, one character consists of up to 8 bits.
● For receive:
DMA transfers data from the receive FIFO to the address where the data received is to
be stored. The reception process with DMA occurs when the receive FIFO contains at
least one character. When the receive FIFO is empty, then DMA goes into wait state
until there is at least one character in the receive FIFO for the reception process to
occur. In receive mode, one character consists of up to 12 bits.
The burst transfer and single transfer request signals are not mutually exclusive, so
they can both be asserted at the same time. For example, when there is more data than
the watermark level in the receive FIFO, the burst transfer request and the single
transfer request are asserted. When the amount of data left in the receive FIFO is less
than the watermark level, only the single request is asserted. This is useful for
situations where the number of characters left to be received in the stream is less than
a burst.
8.1
DMA operation
First of all, the DMA clock is enabled. In transmission, the TX interrupt is enabled. Then,
DMA is enabled by the DMACConfiguration register. Setting the relevant bit in the
DMACIntTCClear register or in the DMACIntErrClr register, respectively, clears the interrupt
request. The DMA channel to be used is selected, corresponding to which the registers of
that channel are configured. For example, channel 0 is selected, then the DMACC0SrcAddr
register contains the source address of the data which is to be transmitted.
DMACC0DestAddr register contains the address of TX FIFO.
In reception, the RX interrupt is enabled. Then DMA is enabled and all the pending
interrupts on DMA are cleared. For channel 0, the DMACC0SrcAddr contains the address of
RX FIFO and DMACC0DestAddr contains the address where the data is to be received.
Doc ID 16862 Rev 2
19/30