AN3114 Datasheet, PDF (19/43 Pages) STMicroelectronics – This application note describes techniques for connecting

AN3114
Integrated LCD controller
Figure 11. Medium+ and high density LCD controller block diagram
FREQUENCY GENERATOR
LCDCLK
FREQUENCY GENERATOR
16-bit Prescaler
LCDCLK
LCDCLK/65536
LCD REGS ^PS[3:0]
DIV[3:0]
LCD RAM
(44x8 bits)
CLOCK MUX
ck_ps
Divide by 16 to 31
ck_div
SEG
DRIVER
COM
DRIVER
SEG[43:0]
44
Interrupt
COM[7:0]
COMMON/SEGMENT DRIVER
LCD REGS
VSEL
EN
STATIC
READY
PULSE GEN
HD
BIAS[1:0]
CC[2:0]
VOLTAGE
GENERATOR
CONTRAST
CONTROLLER
Analog booste r
V_SS
1/3-1/4 V_LCD
2/3 -3/4V_LCD
1/2 V_LCD
V_LCD
CONTRAST CONTROLLER
COM0
Analog
switch
array
COM7
SEG0
SEG43
I/O Ports
BJC
3.1.1
Frequency generator block
The first block of the LCD controller is the frequency generator. It consists of a 16-bit ripple
counter prescaler and a programmable clock divider with a divider factor ranging from 16 to
31. It generates the LCD frequency, ck_div, starting from the input clock frequency, f_LCDCLK.
The 16-bit prescaler divides f_LCDCLK by 1 up to 65536. The value can be configured through
the PS[3:0] bits in the LCD_FRQ register. If a finer resolution rate is required, a second
divider can be used to further divide fck_ps by a factor of 16 to 31. This second factor is
configured through the DIV[3:0] bits in the LCD_FRQ register. fck_div is given by the
following equation:
f_{ck_div} = ₂----_P----_S----^f_×--^C---₍-^L-₁--^K--₆-^L---^C-+---^D-_D-----_I--_V-----₎
Doc ID 16829 Rev 3
19/43