AN2442 Datasheet, PDF (19/22 Pages) STMicroelectronics – Using the STR91xFA DMA controller

AN2442
DMA transfer examples
TIM0 is configured in PWM input mode. At each Input Capture1 event a transfer from
registers IC1R and IC2R to memory will occur.
To store ICR1 and ICR2 related to the same input capture event, use two channels;
channel0 to transfer the IC1R value and channel 1 to transfer the IC2R value.
A pattern can be used as the external signal to be sure that their pulse widths and periods
correspond with those stored in the memory.
TIM1 configured in PWM mode can generate such a pattern if its period and pulse width are
modified every output compare interrupt with the desired values.
To obtain the time values:
IC1R x tPRESC
Period =
fPCLK
2.6.3
IC2R x tPRESC
Pulse =
fPCLK
Where:
fPCLK = Internal clock frequency
tPRESC = Timer clock prescaler
Transfer properties
● The flow controller is DMAC.
● The transfer type: Peripheral to memory.
● DMAC is triggered by the Input capture1 event request.
● Burst transfers are not supported since there is no FIFO inside.
● Linked mode is used (see next section for details).
● Source and destination address not incremented.
2.6.4
Use of linked lists for DMA transfer
Linked lists is used due to the fact that the content of the two input capture registers
changes every time depending on the external signal. It is therefore possible to save these
values separately at each input capture event which gives more information about the
injected signal.
One linked list is used for each channel; link1 for channel0 and link2 for channel1. Therefore
linked list1 is used to transfer IC1R values to TIM-IC1R buffer and linked list2 to transfer
IC2R values to TIM-IC2R buffer (refer to Figure 8.).
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