ST10F276_06 Datasheet, PDF (181/229 Pages) STMicroelectronics – 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM

ST10F276
Electrical characteristics
1. This specification is not valid for outputs which are switched to open drain mode. In this case the
respective output floats and the voltage is imposed by the external circuitry.
2. Port 5 leakage values are granted for not selected A/D converter channel. One channels is always
selected (by default, after reset, P5.0 is selected). For the selected channel the leakage value is similar to
that of other port pins.
3. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific
test modes) implemented on input path. Pay attention to not stress P2.0 input pin with negative overload
beyond the specified limits: Failures in Flash reading may occur (sense amplifier perturbation). Refer to
next Figure 44 for a scheme of the input circuitry.
4. Not 100% tested, guaranteed by design characterization.
5. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any
pin exceeds the specified range (that is, V_OV > V_DD + 0.3V or V_OV < –0.3V). The absolute sum of input
overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the
specified limits.
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected if
they are used for CS output and the open drain function is not enabled.
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
9. The power supply current is a function of the operating frequency (f_CPU is expressed in MHz). This
dependency is illustrated in the Figure 45 below. This parameter is tested at V_DDmax and at maximum CPU
clock frequency with all outputs disconnected and all inputs at V_IL or V_IH, RSTIN pin at V_IH1min: This
implies I/O current is not considered. The device is doing the following:
- Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): No output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
10. The power supply current is a function of the operating frequency (f_CPU is expressed in MHz). This
dependency is illustrated in the Figure 45 below. This parameter is tested at V_DDmax and at maximum CPU
clock frequency with all outputs disconnected and all inputs at V_IL or V_IH, RSTIN pin at V_IH1min: This
implies I/O current is not considered. The device is doing the following:
- Fetching code from all sectors of both IFlash and XFlash, accessing in read (few fetches) and write to
XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): No output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
11. The Idle mode supply current is a function of the operating frequency (f_CPU is expressed in MHz). This
dependency is illustrated in the Figure 44 below. These parameters are tested and at maximum CPU clock
with all outputs disconnected and all inputs at V_IL or V_IH, RSTIN pin at V_IH1min.
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 to
0.1V or at V_DD – 0.1V to V_DD, V_AREF = 0V, all outputs (including pins configured as outputs) disconnected.
Furthermore, the Main Voltage Regulator is assumed off: In case it is not, additional 1mA shall be
assumed.
181/229