TDA7421 Datasheet, PDF (18/38 Pages) STMicroelectronics – AM/FM TUNER FOR CAR RADIO AND Hi-Fi APPLICATIONS

TDA7421
A start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any command and initiate a data transfer onto the
bus.
The TDA7421 continuously monitors the SDA
and SCL lines for a valid START and will not re-
sponse to any command if this condition has not
been met.
Stop condition
A STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a
stable HIGH level. This condition terminate the
communication between the devices and force’s
the bus interface of the TDA7421 into the initial
condition.
Acknowledge
Indicates a successful data transfer. The trans-
mitter will release the bus after sending 8 bit of
data. During the 9th clock cycle the receiver will
pull the SDA line to LOW level to indicate it has
received the eight bits of data correctly.
Data transfer
During data transfer the TDA7421 samples the
SDA line on the leading edge of the SCL clock,
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
Device Addressing
To start the communication between two devices,
the bus master must initiate a start instruction se-
quence, followed by an eight bit word corre-
sponding to the address of the device it is ad-
dressing. The most significant 6 bits of the slave
address identify the device type.
The TDA7421 device code is fixed as "110001".
The next significant bit is used either to address
the tuner section (1) or the PLL section (0) of the
chip.
Following a START condition the master sends
slave address word; the TDA7421 will "acknow-
ledge" after this first transmission and wait for a
second word (the word address field).
This 8 bit address field provides an access to any
of the 8 internal addresses. Upon receipt of the
word address the TDA7421 slave device will re-
spond with an "acknowledge".
At this time, all the following words transmits to
the TDA7421 will be considered as data.
The internal address will be automatically incre-
mented. After each word receipt the TDA7421 will
answer with an "acknowledge".
The interface protocol comprises:
– a subaddress byte
– a sequence of data (N-bytes + acknowledge)
– a stop condition (P)
– a start condition (S)
– a chip address byte
CONTROL REGISTER FUNCTION
REGISTER NAME
PC
RC
IRC
IFCM
EW
IFENA
CF
IFS
PM
D
LPIN1/2
A
B
LDENA
CURRH
FUNCTION
Programmable Counter for VCO Frequency
Reference Counter PLL
Reference Counter IF
IF Counter Mode
Frequency Error Window
Enable IF Counter
Center Frequency IF Counter
Sampling Time IF Counter
Stby, FM, AM, AM swallow mode (PLL Mode)
Programmable Delay for Lock Detector
Loop Filter Input Select
Charge Pump High Current
Charge Pump Low Current
Lock Detector Enable
Set Current High
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