TDA7407_07 Datasheet, PDF (18/46 Pages) STMicroelectronics – Advanced car signal processor

Noise blanker part
TDA7407
Table 7. Noise blanker electrical characteristics (continued)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
T_S
Suppression pulse
duration ⁽⁶⁾
Signal HOLDN in
testmode
Noise rectifier
V_RECTADJ discharge adjustment
(7)
Signal PEAK in
testmode
SR_PEAK
Noise rectifier charge
Signal PEAK in
testmode
Noise rectifier
V_ADJMP adjustment through
multipath ⁽⁹⁾
Signal PEAK in
testmode
BLT = 00 TBD
BLT = 10 TBD
BLT = 01 TBD
BLT = 00 TBD
NRD = 00 ^{(5) (10)}
NRD = 01 ^{(5) (10)}
NRD = 10 ^{(5) (10)}
NRD = 11 ^{(5) (10)}
PCH = 0 ^{(8) (10)}
PCH = 1 ^{(8) (10)}
MPNB = 00 ^{(9) (10)}
MPNB = 01 ^{(9) (10)}
MPNB = 10 ^{(9) (10)}
MPNB = 11 ^{(9) (10)}
38
32
25.5
22
0.3
0.8
1.3
2.0
10
20
0.3
0.5
0.7
0.9
TBD μs
TBD μs
TBD μs
TBD μs
(10) _V/ms
(10) _V/ms
(10) _V/ms
(10) _V/ms
(10) _mV/μs
(10) _mV/μs
(10) _V/ms
(10) _V/ms
(10) _V/ms
(10) _V/ms
1. All Thresholds are measured using a pulse with TR =2ms, THIGH = 2ms and TF = 10ms. The repetition
rate must not increase the PEAK voltage
2. NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold
3. NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment
4. OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector
5. FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control
6. BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment
7. NRD represents the Configuration Byte bit pair D1, D0 for the noise rectifier discharge adjustment
8. PCH represents the Stereo decoder Byte bit D5 for the noise rectifier charge current adjustment
9. MPNB represents the HighCut Byte bit D7 and the Fieldstrength Byte D7 for the noise rectifier multipath
adjustment
10. By design / characterization functionally guaranteed through dedicated test mode structure
Figure 3. Vn timing diagram
VIN
VOP
DC
D97AU636
TR THIGH
TF
Time
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