STM32L152C8T6 Datasheet, PDF (18/131 Pages) STMicroelectronics – Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

Functional overview
STM32L151x6/8/B, STM32L152x6/8/B
Nested vectored interrupt controller (NVIC)
The ultralow power STM32L15xxx embeds a nested vectored interrupt controller able to
handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
3.3.1
3.3.2
Reset and supply management
Power supply schemes
• V_DD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through V_DD pins.
• V_SSA, V_DDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to V_DDA is 1.8 V when the ADC is used).
V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the V_DD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V_DD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V_DD at least 1 ms after it exits
the POR area.
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DocID17659 Rev 9