PSD913F2 Datasheet, PDF (18/94 Pages) STMicroelectronics – Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD9XX Family
8.0
PSD9XX
Register
Description
and Address
Offset
Preliminary Information
Table 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD9XX registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 7. Register Address Offset
Register Name Port A Port B Port C Port D Other*
Data In
00 01 10 11
Description
Reads Port pin as input,
MCU I/O input mode
Control
02 03
Selects mode between
MCU I/O or Address Out
Data Out
04 05 12 13
Stores data for output
to Port pins, MCU I/O
output mode
Direction
06 07 14 15
Configures Port pin as
input or output
Drive Select
08 09 16 17
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Flash Protection
C0
Read only – Flash Sector
Protection
Secondary Flash
Protection
Read only – PSD Security
C2
and Secondary Flash
Sector Protection
PMMR0
B0
Power Management
Register 0
PMMR2
B4
Power Management
Register 2
Page
E0 Page Register
Places PSD memory
VM
E2
areas in Program and/or
Data space on an
individual basis.
*Other registers that are not part of the I/O ports.
14