M25P05 Datasheet, PDF(18/32 Page) STMicroelectronics – 512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

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M25P05 Datasheet, PDF (18/32 Pages) STMicroelectronics – 512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

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M25P05

Figure 16. Deep Power-down (DP) Sequence

01234567

tDP

Instruction

Stand-by Mode Deep Power-down Mode

AI03753C

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in the lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Erase instructions.

Driving Chip Select (S) High deselects the device,

and puts the device in the Standby mode (if there

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instruction,

to reduce the standby current (from ICC1 to ICC2,

as specified in Table 13).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) instruction also allows the Electronic Signa-

ture of the device to be output on Serial Data Out-

put (Q).

The Deep Power-down mode automatically stops

at Power-down, and the device always Powers-up

in the Standby mode.

The Deep Power-down (DP) instruction is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D). Chip Se-

lect (S) must be driven Low for the entire duration

of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise the Deep Power-down (DP) instruc-

tion is not executed. As soon as Chip Select (S) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any effects on the cycle that

is in progress.

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