AN3324 Datasheet, PDF (18/37 Pages) STMicroelectronics – Implementing power-on self tests

AN3324
Module software requirements for non applicative peripherals
3.7
Clock Monitor Unit (CMU)
The main task of the Clock Monitor Unit (CMU) is to supervise the integrity of various clock
sources.
User software has to manage the following conditions:
● Loss of external crystal oscillator clock
● FMPLL frequency higher than a (programmable) value set as high reference
● FMPLL frequency lower than a (programmable) value set as low reference
SPC56EL60 includes three CMUs:
a) CMU_0 to monitor the clock signal of the Sphere of Replication (SoR) and the
clock from the crystal oscillator
b) CMU_1 to monitor the clock signal used by the Motor Control related peripherals
(eTimer, FlexPWM, CTU, and ADC)
c) CMU_2 to monitor the clock signal for the protocol engine of the FlexRay module
Use of the CMU is mandatory: if the related modules are used by the application safety
function, the user must verify that the CMUs are not disabled and their faults managed by
the FCCU.
Note:
In general, the following two application-dependent configurations must be executed before
CMU monitoring can be enabled.
1 Crystal oscillator clock monitor (only CMU_0): the software must configure the RCDIV field
of the Control Status register (CMU_0_CSR) with a value related to the external oscillator
frequency.
2 Clock signal monitors (CMU_1, CMU_2): the CMU_x_HFREFR and CMU_x_LFREFR
registers must be configured depending on the SoR, Motor Control, and FlexRay clock
frequencies.
To later enable the CMUs, the flag CME in the respective Control Status Register
(CMU_x_CSR) must be asserted.
3.8
Note:
Note:
Frequency-Modulated Phase-Locked Loop (FMPLL)
Application software has to check that the system uses the system FMPLL clock as system
clock before running any safety element function.
Application software can verify the current system clock by checking the S_SYSCLK flag of
the ME_GS register. S_SYSCLK equal to 0x4 indicates that the system FMPLL clock is
used as system clock.
Each FMPLL provides a loss of lock error indication that is routed to the RGM (see
Section 3.4: Reset Generation Module (MC_RGM)) and the FCCU (see Section 3.5: Fault
Collection and Control Unit (FCCU)).
The application software has to enable the respective fault and configure the FCCU to
manage it. Since in case of fault the system clock can be driven by the internal RC oscillator
(see Section 3.9: Internal RC Oscillator (IRCOSC)), the fault of the FMPLL is considered as
Non-Critical Fault.
The pll_fail output is not masked (pll_fail_mask flag in the FMPLL_x Control Register (CR)
deasserted). To enable the RGM input related to FMPLL loss of clock, the registers
RGM_FERD and RGM_FEAR must be configured. To enable the FCCU fault path some
Doc ID 18311 Rev 2
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