ST72361XX Datasheet, PDF (175/279 Pages) STMicroelectronics – Clock, reset and supply management

ST72361xx-Auto
LINSCI serial communication interface (LIN master/slave)
Figure 81. SCI block diagram in LIN slave mode
TDO
RDI
Write
Read
(DATA REGISTER) SCIDR
Transmit Data Register (TDR)
Received Data Register (RDR)
Transmit Shift Register
Receive Shift Register
SCICR1
R8 T8 SCID M WAKE PCE PS PIE
TRANSMIT
CONTROL
WAKE
UP
UNIT
SCICR2
TIE TCIE RIE ILIE TE RE RWU SBK
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
TDRE TC RDRF IDLE
OR/
LHE
NF
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
f_CPU
LIN SLAVE BAUD RATE
AUTO SYNCHRONIZATION
UNIT
SCIBRR
LPR7
LPR0
f_{CPU / LDIV}
/16
SCICR3
LDUM LINE LSLV LASE LHDM LHIE LHDF LSF
CONVENTIONAL BAUD RATE
GENERATOR
+
EXTENDED PRESCALER
0
1
LIN SLAVE BAUD RATE GENERATOR
15.9.3
LIN reception
In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features
for handling the LIN header automatically (identifier detection) or semiautomatically (synch
break detection) depending on the LIN Header detection mode. The detection mode is
selected by the LHDM bit in the SCICR3.
Additionally, an automatic resynchronization feature can be activated to compensate for any
clock deviation, for more details please refer to LIN baud rate.
LIN header handling by a slave
Depending on the LIN header detection method the LINSCI will signal the detection of a LIN
Header after the LIN synch break or after the Identifier has been successfully received.
Doc ID 12468 Rev 3
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