TDA7501_07 Datasheet, PDF (17/29 Pages) STMicroelectronics – Line driver for digital car radio Signal processor (DSPLD)

TDA7501
7
SPI bus mode
SPI bus mode
7.1
Interface protocol
The TDA7501 SPI interface protocol comprises :
● a subaddress and
● a sequence of n databytes
each consisting of 8 bits (see Figure 14).
The interface accepts both a positiv (Cpol = 1, Cpha = 1) as well as a negativ (Cpol = 0,
Cpha = 0) clocking scheme. However, the data transmitted has to be valid on the rising
edges of the serial clock SCL.
Figure 14. Timing diagram for the SPI bus mode.
SEL
SCL
Cpol=1
SCL
Cpol=0
SDA
SA3 SA2 SA1 SA0
SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
DATA
D7 D6 D5 D4 D3 D2 D1 D0
DATA-n
D00AU1209
Table 5.
Symbol
Switching characteristics (SPI mode)
Parameter
f_SCLK Serial input clock frequency (SCL)
T_su
Serial data setup time
T_hld
Serial data hold time
T_wh
Serial clock high time width
T_wl
Serial clock low time width
T_scl
Select (SEL) to select (SCL) falling setup time
T_rel
Select (SCL) to select (SEL) rising release time
t_r
Data rise time
t^f
Data fall time
T_sh
Chip select high time
Min.
0
40
40
100
100
200
200
200
Typ.
Max.
4.0
2
2
Unit
MHz
ns
ns
ns
ns
ns
ns
ms
ms
ns
Figure 15. Timing diagram for switching characteristic
Tscl
Tsu Thld
Twh
Twl
Trel
Tsh
SEL
SCL
SDA
SAx,Dy
D00AU1208
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