STOTG04ES Datasheet, PDF (17/26 Pages) STMicroelectronics – USB-OTG Full-speed Transceiver

STOTG04ES
Block description
Table 15. UART drivers direction
bdir[1]
0
0
1
1
bdir[0]
0
1
0
1
DAT_VP ↔ D+
→
→
←
←
SE0_VM ↔ D-
→
←
→
←
6.7.4 Audio mode
In this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the D+, D-
and ID pins, leaving them in a high impedance state. This allows these lines to be used for transmission
of audio signals. The transceiver should not provide voltage on its V_BUS output in this mode. Conditions
described in Table 16 force the transceiver into the audio mode.
Table 16. Audio mode setup
transp_en bit
0
uart_en bit
0
OE_TP_INT/ signal
1
Control Register 2
00000000
6.8 Registers
The STOTG04ES transceiver device is controlled using register settings (see Table 17). These registers
can be set and read via the I²C bus.
Table 17. Register set
Register
Size (bits) _Acc ⁽¹⁾
Addr ⁽²⁾
Description
Vendor ID
16
Product ID
16
Control 1
8
Control 2
8
Control 3
8
Interrupt Source
8
Interrupt Latch
8
Interrupt Mask False
8
Interrupt Mask True
8
r
00h STMicroelectronics ID (0483h) - LSB first
r
02h ID of the STOTG04 (A0C4h) - LSB first
r/s/c
04h 05h First Control Register
r/s/c
06h 07h Second Control Register
r/s/c
12h 13h Third Control Register
r
08h Current state of signals generating interrupts
r/s/c
0Ah 0Bh Latched source that generated interrupt
r/s/c
0Ch 0Dh Enables interrupts on falling edge
r/s/c
0Eh 0Fh Enables interrupts on rising edge
(1) Access type can be: read (r), set (s), clear (c).
(2) The first address is to set, the second one to clear bits.
When writing to the set address, any “1” will set the associated Bit to logic “1”. When writing to the clear
address, any “1” will set the associated Bit to logic “0”. It is possible to read from any address, whether it
is a set or clear address. See Tables 18, 19, 20, 21 for bit setting details.
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