STM32F103ZET7 Datasheet, PDF (17/130 Pages) STMicroelectronics – High-density performance line ARM-based 32-bit MCU

STM32F103xC, STM32F103xD, STM32F103xE
Description
2.3.10
2.3.11
2.3.12
2.3.13
Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
Power supply schemes
● V_DD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through V_DD pins.
● V_SSA, V_DDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
is used). V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.
● V_BAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V_DD is not present.
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V_DD is below a specified threshold, V_POR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is higher
than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics for the values of
V_POR/PDR and V_PVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop modes.
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
Doc ID 14611 Rev 8
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