MTC20154 Datasheet, PDF (17/21 Pages) STMicroelectronics – INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT

MTC20154
Table 21. Receive / Transmit Protocol
Symbol
Parameters
min
typ
max
Ts
Setup Time
7 ns
–
–
Th
Hold time
0.2 ns
–
–
TDv
Data Valid
0.5 ns
–
4 ns
Data set up and hold time are specified versus rising edge of CLKM
Remarks
Receive / Transmit Interface
The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output
signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328 MHz data lines in the following
table.
If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode), and
all the RXi, TXi, CLKWD periods are twice as long as in normal mode.
Table 22. Receive / Transmit Protocol
RXD0 / TXD0 will contain
RXD1 / TXD1 will contain
RXD2 / TXD2 will contain
RXD3 / TXD3 will contain
N0
N1
N2
N3
b0
b4
b8
b12
b1
b5
b9
b13
b2
b6
b10
b14
b3
b7
b11
b15
TX / TXE Signal Dynamic Range
The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit repre-
sentation coming from the digital processor. The maximal positive number is 2¹⁴-1, the most negative
number is -2¹⁴, the 3 LSBs are ignored. Any signal exceeding these limits is clamped to the maximal value.
Figure 10. TX/TXE Bit Map
sign sign b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 n.u. n.u. n.u.
RX Signal Dynamic Range
The dynamic range of the signal from the ADC is limited to 13 bits. Those bits are converted to a signed
representation with a maximal positive number of 2 ¹⁴-1 and a most negative number of 2 ¹⁴. The 2 LSBs
are filled with ’0’.
Figure 11. RX Bit Map
sign b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0
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