M58LW064D Datasheet, PDF(17/50 Page) STMicroelectronics – 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory

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M58LW064D Datasheet, PDF (17/50 Pages) STMicroelectronics – 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory

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M58LW064D

Table 4. Commands

Bus Operations

Command

1st Cycle

2nd Cycle

Subsequent

Final

Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data

Read Memory Array â¥ 2 Write X FFh Read RA

Read Electronic Signature â¥ 2 Write X 90h Read IDA(2) IDD(2)

Read Status Register

2 Write X 70h Read X

SRD

Read Query

â¥ 2 Write X 98h Read QA(3) QD(3)

Clear Status Register

1 Write X 50h

Block Erase

2 Write X 20h Write BA

Word/Byte Program

2 Write X

40h

10h

Write

Write to Buffer and

Program

4 + N Write BA E8h Write BA

N Write PA PD Write X D0h

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Block Protect

2 Write X 60h Write BA 01h

Blocks Unprotect

2 Write X 60h Write X

D0h

Protection Register

Program

2 Write X C0h Write PRA PRD

Configure STS command 2 Write X B8h Write X

Note: 1. X Donât Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program

Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, PRA Protection register address,

PRD Protection Register Data, CC Configuration Code.

2. For Identifier addresses and data refer to Table 6., Read Electronic Signature.

3. For Query Address and Data refer to APPENDIX B., COMMON FLASH INTERFACE - CFI.

Table 5. Configuration Codes

Configuration

Code

DQ1

DQ2

Mode

STS Pin

VOL during P/E

00h

0 Ready/Busy

operations

Hi-Z when the

memory is ready

01h

Pulse on Erase

complete

Pulse on

Pulse Low then

02h

0 Program

High when

complete

operation

completed(2)

Pulse on Erase

03h

1 or Program

complete

Note: 1. DQ2-DQ7 are reserved

2. When STS pin is pulsing it remains Low for a typical time of 250ns.

Description

The STS pin is Low during Program and

Erase operations and high impedance when

the memory is ready for any Read, Program

or Erase operation.

Supplies a system interrupt pulse at the end

of a Block Erase operation.

Supplies a system interrupt pulse at the end

of a Program operation.

Supplies a system interrupt pulse at the end

of a Block Erase or Program operation.

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