L6668 Datasheet, PDF (17/23 Pages) STMicroelectronics – SMART PRIMARY CONTROLLER

Figure 41. Hiccup-mode OCP: timing diagram
Vcc
Vcc _ON
Vcc _OFF
re
V _CS
1.5 V
Secondary diode is shorted here
OUT
L6668
t
t
OCP latch
t
Vcc_OK
t
t
A second comparator senses the voltage on the current sense input and shuts the IC down if the voltage
at the pin exceeds 1.5 V. Such an anomalous condition is typically generated by either a short circuit of
the secondary rectifier or a shorted secondary winding or a saturated flyback transformer.
This condition is latched as long as the IC is supplied. When the IC is disabled, however, no energy is
coming from the self-supply circuit, then the voltage on the Vcc capacitor will decay and cross the UVLO
threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc
voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the IC re-
started.
Ultimately, either of the above mentioned failures will result in a low-frequency intermittent operation (Hic-
cup-mode operation), with very low stress on the power circuit. The timing diagram of figure 41 illustrates
this operation.
4.6 Power Management
The L6668 is specifically designed to minimize converter's losses under light or no-load conditions, and a
special function has been provided to help the designer meet energy saving requirements even in power-
factor-corrected systems where a PFC pre-regulator precedes the DC-DC converter.
Actually EMC regulations require compliance with low-frequency harmonic emission limits at nominal
load, no limit is envisaged when the converter operates with a light load. Then the PFC pre-regulator can
be turned off, thus saving the no-load consumption of this stage (0.5 to 1W).
To do so, the device provides the PFC_STOP (#14) pin: it is an open collector output, normally low, that
becomes open when the voltage V_COMP falls below 2.2V.
This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in
figure 42. To prevent intermittent operation of the PFC stage, 0.5V hysteresis is provided: the PFC_STOP
pin is re-asserted low (which will re-enable the PFC pre-regulator) when V_COMP exceeds 2.7 V.
A capacitor (and a limiting resistor in the hundred ohms), shown in dotted lines, may be used if one wants
to delay PFC turn-off
When the L6668 is in UVLO (Vcc<8.7V) the pin is kept high so as to ensure that the PFC pre-regulator
will start up only after the DC-DC converter governed by the L6668 is activated.
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