AN2797 Datasheet, PDF (17/23 Pages) STMicroelectronics – PCB layout guidelines for SPEAr600

AN2797
GPIO and CLD interface considerations
4
GPIO and CLD interface considerations
There are no stringent requirements for GPIO or CLD interfaces, but some precautions
should be considered for some applications that employ very wide buses switching
simultaneously, or have electrically long interconnects, such as signal traces 1 ns or longer.
These conditions apply heavy loading to the power distribution network supplying these
I/Os, and it is imperative that good decoupling practices are used for the 3.3 V supply. See
Appendix A for decoupling capacitor layout guidelines. When wide buses or long interfaces
are necessary, 22 Ohm series resistors placed close to SPEAr provide additional benefit by
reducing the loading seen by the I/Os.
Doc ID 14841 Rev 1
17/23