STM32L443CC Datasheet, PDF (165/207 Pages) STMicroelectronics – Batch acquisition mode

STM32L443CC STM32L443RC STM32L443VC
Electrical characteristics
Table 80. WWDG min/max timeout value at 80 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
0
0.0512
3.2768
2
1
4
2
8
3
0.1024
0.2048
0.4096
6.5536
ms
13.1072
26.2144
6.3.26
Communication interfaces characteristics
I²C interface characteristics
The I2C interface meets the timings requirements of the I²C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V_DDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 81. I2C analog filter characteristics⁽¹⁾
Symbol
Parameter
Min
Max
Maximum pulse width of spikes
t_AF
that are suppressed by the analog
filter
50⁽²⁾
260⁽³⁾
1. Guaranteed by design.
2. Spikes with widths below t_AF(min) are filtered.
3. Spikes with widths above t_AF(max) are not filtered
Unit
ns
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